Method and associated apparatus for clock-data edge alignment

ABSTRACT

An edge alignment apparatus includes: a signal source, for generating a first and a second square wave signals; a phase delay circuit, for receiving the first and the second square wave signals to generate a delayed first and a delayed second square wave signals; a data circuit, for generating a third square wave signal according to the delayed second square wave signal; and a phase calibrating circuit, for receiving the third square wave signal and the delayed first squared wave signal to generate at least one phase tuning signal to the phase delay circuit for tuning a phase difference between the delayed first and the delayed second square wave signals, such that a signal edge of the third square wave signal aligns with that of the first square wave signal. The first, second and third square wave signals have a same frequency.

This application claims the benefit of Taiwan application Serial No.101116944, filed May 11, 2012, the subject matter of which isincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates in general to a method and associated apparatusfor signal control, and more particularly to a method and associatedapparatus for clock-data edge alignment.

2. Description of the Related Art

FIG. 1 shows a schematic diagram of a conventional signal transmitter.In the transmitter, a digital signal D in a KHz level is converted by adigital-to-analog converter (DAC) 102 into an analog signal A, which isthen inputted into a mixer 110. Through a local oscillation (LO) signalgenerated by a local oscillator 112, the analog signal A inputted intothe mixer 110 is up-converted to a radio-frequency (RF) signal in alevel of GHz, which is then amplified by a high-output frequencyamplifier 114 and outputted as an amplified RF signal A_(RF).

A radio-frequency digital-to-analog converter (RFDAC), or referred to asa digital power amplifier, is now available for replacing functions ofthe above signal transmitter to directly generate a large-power RFsignal. FIG. 2 shows a schematic diagram of an RFDAC. An RFDAC 200includes an input as an N-bit digital signal D bus and an LO input. Allinput signals including the N-bit digital signal D and the LO signal arefundamentally GHz signals, according to which the RFDAC 200 is capableof generating an RF signal.

In addition to having the same frequency, signal edges between all ofthe input signals also need to be aligned to prevent output powerdegradation and noise increase in the RFDAC 200. Therefore, there is aneed for a solution capable of effectively aligning signal edges betweenthe input signals.

SUMMARY OF THE INVENTION

An edge alignment apparatus is provided by the present invention. Theedge alignment apparatus comprises a signal source, for generating afirst square wave signal and a second square wave signal; a phase delaycircuit, for receiving the first square wave signal and the secondsquare wave signal to generate a delayed first square wave signal and adelayed second square wave signal; a data circuit, for generating athird square wave signal according to the delayed second square wavesignal; and a phase calibrating circuit, for receiving the third squarewave signal and the delayed first squared wave signal to generate atleast one phase tuning signal to the phase delay circuit for tuning aphase difference between the delayed first and the delayed second squarewave signals, such that a signal edge of the third square wave signalaligns with a signal edge of the first square wave signal. The first,second and third square wave signals have a same frequency.

An edge alignment method, for aligning signal edges of a delayed firstsquare wave signal and a delayed second square wave signal, is furtherprovided by the present invention. The method comprises steps of: a)receiving a first square wave and a second square wave; b) generating adelayed first square wave and a delayed second square wave according toat least one phase tuning signal; c) sampling the delayed second squarewave signal according to the delayed first square wave signal togenerate a sampling signal; and d) changing the at least one phasetuning signal when a bitstream in the sampled signal is not a metadataand returning to step (b), and stopping changing the at least one phasetuning signal when the bitstream is the metadata.

An edge alignment method, for aligning signal edges of a delayed firstsquare wave signal and a delayed second square wave signal, is furtherprovided by the present invention. The method comprises steps of:receiving a first square wave and a second square wave; generating adelayed first square wave and a delayed second square wave according toat least one phase tuning signal; sampling the delayed second squarewave signal according to the delayed first square wave signal togenerate a sampling signal; and determining a first state or a secondstate when a bitstream in the sampling signal is not a metadata, ordetermining a third state when the bitstream is the metadata. Inaccordance with this embodiment, the at least one phase tuning signalcomprises N bits, and a plurality of third states are obtained afterchanging the at least one phase tuning signal 2^(N) times, and anoptimal phase tuning signal is determined from a plurality of phasetuning signals corresponding to the third states.

The above and other aspects of the invention will become betterunderstood with regard to the following detailed description of thepreferred but non-limiting embodiments. The following description ismade with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (prior art) is a schematic diagram of a conventional transmitter;

FIG. 2 (prior art) is a schematic diagram of a radio-frequencydigital-to-analog converter (RFDAC);

FIGS. 3A to 3C are respectively a clock-data signal edge alignmentapparatus according to first to third embodiments of the presentinvention;

FIGS. 4A to 4D are schematic diagrams of a first tuning stage, a secondtuning stage and a third tuning stage;

FIG. 5 is a schematic diagram of a sampling circuit;

FIG. 6 is a flowchart of a signal edge alignment method according to oneembodiment of the present invention; and

FIGS. 7A to 7C are flowcharts of a control process for a phase tuningsignal in signal edge alignment method according to one embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3A shows a clock-data signal edge alignment apparatus according toa first embodiment of the present invention. The edge alignmentapparatus calibrates the signal edge of all input signals inputted intoa radio-frequency digital-to-analog converter (RFDAC) 360. The edgealignment apparatus comprises a clock source 310, a phase delay circuit315, a data circuit 340 and phase calibration circuit 350. The phasedelay circuit 315 comprises a first phase delay unit 320 and a secondphase delay unit 330. The phase calibrating circuit 350 comprises asampling unit 352 and an alignment loop state machine 354.

The clock source 310 generates a first clock signal CK1 a and a secondclock signal CK2 a having a same frequency. The first clock signal CK1 ais inputted into the first phase delay unit 320, and the phase of thefirst clock signal CK1 a is delayed according to a first phase tuningsignal T1 to generate a delayed version of the first clock signal, CK1b. Similarly, the second clock signal CK2 a is inputted into the seconddelay unit 330, and the phase of the second clock signal CK2 a isdelayed according to a second phase tuning signal T2 to generate adelayed version of the second clock signal, CKb2. The delayed firstclock signal CK1 b may be regarded as an LO signal inputted into theRFDAC 360.

The data circuit 340 receives the delayed second clock signal CKb2 togenerate N-bit digital signals D1 to DN. That is, the N-bit digitalsignals D1 to DN and the delayed second clock signal CKb2 have the samefrequency, and a signal edge of the N-bit digital signals D1 to DN isaligned with a signal edge of the delayed second clock signal CKb2.

The signal edges of the N-bit digital signals D1 to DN and the delayedfirst clock signal CK1 b need to be aligned when the N-bit digitalsignals D1 to DN and the delayed first clock signal CK1 b are inputtedinto the RFDAC 360. Thus, the phase calibrating circuit 350 tunes thephase of the delayed first clock signal CK1 b and the delayed secondclock signal CK2 b, so that the signal edges of N-bit digital signals D1to DN align with the signal edge of the delayed first clock signal CK1b.

According to one embodiment of the present invention, the phasecalibrating circuit 350 receives the delayed first clock signal CK1 band an x^(th)-bt signal Dx in the digital signals D1 to DN, where x isany number of 1 to N.

Referring to FIG. 3A, the sampling circuit 352 receives the x^(th)-bitsignal Dx and the delayed first clock signal CK1 b, and generates asampling signal S to the alignment loop state machine 354. The alignmentloop state machine 354 changes the first phase tuning signal T1 and thesecond phase tuning signal T2 according to the sampling signal S, suchthat the phase delay circuit 315 is allowed to tune a phase relationshipbetween the delayed first clock signal CK1 b and the delayed secondclock signal CK2 b. When the phase difference between the delayed firstclock signal CK1 b and the delayed second clock signal CK2 b is zero(i.e., no phase difference), i.e., the signal edges of the delayed firstclock signal CK1 b and the delayed second clock signal CK2 b are alreadyaligned, the phase calibrating circuit 350 stops changing the firstphase tuning signal T1 and the second phase tuning signal T2.

According to the first embodiment of the present invention, the phasedelay unit 320 comprises a first tuning stage 322, a second tuning stage324 and a third tuning stage 326. The first tuning stage 322 is regardedas a coarse tuning stage having a minimum delay tuning period ofapproximately 50 ps (picoseconds); the second tuning stage 324 isregarded as an intermediate tuning stage having a minimum delay tuningperiod of approximately 10 ps; the third tuning stage 326 is regarded asa fine tuning stage having a minimum delay tuning period ofapproximately 3 ps. The second delay unit 330 has a same structure asthat of the first delay 320, and details thereof shall be omittedherein.

The primary objective of the present invention is tuning the phaserelationship between the delayed first clock signal CK1 b and thedelayed second clock signal CK2 b. Thus, the tuning for the phaserelationship can be achieved by merely one phase delay unit. FIG. 3Bshows a clock-data signal alignment apparatus according to a secondembodiment of the present invention. Compared to the first embodiment,in the second embodiment, the second clock signal CK2 a and the delayedsecond clock signal CK2 b are entirely identical. That is to say, thedelayed second clock signal CK2 b generated by delaying the clock signalCK2 a by 0 degree, or the second clock signal CK2 a and the generateddelayed second clock signal CK2 b have the same phase. Since a phasedelay circuit 316 comprises only the first delay unit 320 forcontrolling the phase of the first clock signal CK1 a, no phasedifference exists between the delayed first signal CK1 b and the delayedsecond signal CK2 b.

FIG. 3C shows a clock-data signal alignment apparatus according to athird embodiment of the present invention. Compared to the firstembodiment, in the third embodiment, the first clock signal CK1 a andthe delayed first clock signal CK1 b are entirely identical. That is tosay, the delayed first clock signal CK1 b generated by delaying theclock signal CK1 a by 0 degree, or the second clock signal CK1 a and thegenerated delayed second clock signal CK1 b have the same phase. Since aphase delay circuit 317 comprises only the second delay unit 330 forcontrolling the phase of the second clock signal CK2 a, no phasedifference exists between the delayed second signal CK2 b and thedelayed first signal CK1 b.

FIGS. 4A to 4D show schematic diagrams of a first tuning stage, a secondtuning stage and a third tuning stage. The first, second and thirdtuning stages may be applied to the first phase delay unit 320 and thesecond phase delay unit 330 in the phase delay circuits 315, 316 and317. FIG. 4A shows a schematic diagram of a tuning stage. The firsttuning stage comprises an X phase generator 410 and an X-to-1multiplexer 412. Taking X=4 for example, the X phase generator 410receives a clock signal CK and generates four clock signals with a90-degree phase difference from one another to the X-to-1 multiplexer410. According to a first selection signal T_X, the X-to-1 multiplexer412 selects one of the clock signals as a first output clock signalCK_D1. From the above description, it is known that the first selectionsignal T_X is 2-bit when X=4.

FIG. 4B shows a schematic diagram of a second tuning stage. The secondtuning stage comprises a delay chain formed by multiple buffers. Thedelay chain has an input terminal for receiving a first clock outputsignal CK_D1, and further provides Y differently-phased clock signals toa Y-to-1 multiplexer 422. According to a second selection signal T_Y,the Y-to-1 multiplexer 422 selects one of the clock signals as a secondoutput clock signal CK_D2. From the above description, it is known thatthe second selection signal T_Y is 4-bit when Y=16.

FIG. 4C shows a schematic diagram of another second tuning stage. Thesecond tuning stage comprises a delay chain formed by multiple seriallyconnected differential inverters. The delay chain has an input terminalfor receiving a first clock output signal CK_D1, and further provides Ydifferently-phased clock signals to a Y-to-1 multiplexer 432. Accordingto a second selection signal T_Y, the Y-to-1 multiplexer 432 selects oneof the clock signals as a second output clock signal CK_D2. A minimumdelay period of the differential inverters is approximately 10 ps.

FIG. 4D shows a schematic diagram of a third tuning stage. The thirdtuning stage is also referred to as an interpolator. As shown in FIG.4D, two different driving voltages Vd1 and Vd2 are provided such thatdelay periods of a second output clock signal CK_D2 and a third outputclock signal CK_D3 reach a picosecond level. For example, four drivingvoltage sets are provided, with ratios between the driving voltages Vd1and Vd2 of the four driving voltage sets being different. Thus, by usinga 2-bit third selection signal, the phase difference between the secondoutput clock signal CK_D2 and the third output clock signal CK_D3 can betuned.

It is learned from the above descriptions that the first selectionsignal T_X, the second selection signal T_Y and the third selectionsignal add up to a total of 8 bits, which may be utilized as the firstphase tuning signal T1 or the second phase tuning signal T2 outputted bythe phase calibration circuit 350. In the first phase tuning signal T1or the second phase tuning signal T2, the first two bits may control thefirst tuning stage, the next four bits may control the second tuningstage and the last two bits may control the third tuning stage.According to the first phase tuning signal T1, the phase of the firstclock signal CK1 a may be tuned to the delayed first clock signal CK1 b.Similarly, according to the second phase tuning signal T2, the phase ofthe second clock signal CK2 a may be tuned to the delayed second clocksignal CK2 b. As previously stated, the first selection signal T_X, thesecond selection signal T_Y and the third selection signal add up to atotal of 8 bits, and so the minimum phase delay unit is (360/2⁸)degrees. That is to say, when the first selection signal T_X, the secondselection signal T_Y and the third selection signal add up to a total ofp bits, the minimum phase delay unit is (360/2^(p)) degrees.

FIG. 5 shows a schematic diagram of a sampling circuit. The samplingcircuit comprises a first D-type flip-flop 510, a second D-typeflip-flop 512, and a 2-to-1 multiplexer 514. During the process ofsignal edge alignment, the data circuit 340 needs to be controlled tooutput the x^(th)-bit signal Dx that alternates between “0” and “1”,such that a square wave signal generated by the x^(th)-bit signal Dx andthe first clock signal CK1 b have the same frequency and phase.

As shown in FIG. 5, the first D-type flip-flop 510 has a data inputreceiving the x^(th)-bit signal Dx and a clock input receiving the firstclock signal CK1 b. That is, the delayed first clock signal CK1 b servesas a sampling square wave signal, and the x^(th)-bit signal Dx serves asa sampled square wave signal. The second D-type flip-flop 512 has a datainput receiving the delayed first clock signal CK1 b and a clock inputreceiving the x^(th)-bit signal Dx. That is, the x^(th)-bit signal Dxserves as a sampling square wave signal, and the delayed first clocksignal CK1 b serves as a sampled square wave signal. The 2-to-1multiplexer 514 is coupled to the outputs of the first D-type flip-flop510 and the second D-type flip-flop 512, and selects one of the inputsfrom the first D-type flip-flop 510 and the second D-type flip-flop 512as a sampling signal S according to a sampling selection signal Ss. Inother words, the calibrating circuit may utilize the delayed first clocksignal CK1 b to sample the x^(th)-bit signal Dx to generate the samplingsignal S, or may utilize the x^(th)-bit signal Dx to sample the delayedfirst clock signal CK1 b to generate the sampling signal S. Further, thepresent invention samples the sampled square wave signal according to arising edge of the sampling square wave signal to output the samplingsignal S.

It should be noted that the sampling circuit may only employ the firstD-type flip-flop 510, such that the sampling signal S is generated bysampling the x^(th)-bit signal Dx according to the delayed first clocksignal CK1 b. Alternatively, the sampling circuit may only employ thesecond D-type flip-flop 512, such that the sampling signal S isgenerated by sampling the delayed first clock signal CK1 b according tothe x^(th)-bit signal Dx.

The x^(th)-bit signal Dx and the delayed first clock signal CK1 b havethe same frequency. Therefore, when the two square wave signals are indifferent phases, the bitstream generated by the sampling signal S ismaintained at “1” or “0”. When the bitstream continues to output “1”,the alignment loop state machine 354 is regarded as at a state “1”.Conversely, when the bitstream continues to output “0”, the alignmentloop state machine 354 is regarded as at a state “0”.

According to characteristics of digital circuits, a bitstream generatedby the sample signal S becomes metadata when two square wave signals arein the same phase. That is to say, at this point, whether the data to begenerated by the sampling signal S is “1” or “0” cannot be predicted,and may randomly become “1” or “0’. When the bitstream generated by thesampled data becomes the metadata, the alignment loop state machine 354is regarded as at a state “2’.

FIG. 6 shows a flowchart of a signal edge alignment method according toone embodiment of the present invention. After the calibration processstarts, in Step S610, the alignment loop state machine 354 receives abitstream outputted by the sampling signal S and determines a state. Aspreviously described, the state of the alignment loop state machine is“1” or “0” when two square wave signals (the x^(th)-bit signal Dx andthe delayed first clock signal CK1 b) are in difference phases. When itis determined in Step S612 that that the state is not “2”, Step S614 isperformed. In Step S614, the alignment loop state machine 354 needs tochange a phase tuning signal (the first phase tuning signal T1 or thesecond phase tuning signal T2) to tune the phase difference between thetwo square wave signals.

After the phase tuning signal is changed, Step S610 is iterated, inwhich the bitstream outputted by the sampling signal S is againreceived. When it is confirmed in Step S612 that the state is “2”, thealignment loop state machine 354 then stops changing the phase tuningsignal to achieve two square wave signals adjusted to the same phase.

Many methods for the alignment loop state machine 354 to determinewhether the state is “2” are available, and all determine whether thebitstream generated by the sampling signal S is the metadata. Some ofthe methods are described below.

In a first method, a statistical approach is adopted for determiningwhether data of the bitstream is metadata. For example, multiple bits(e.g., 100 bits) in the sampling signal S are successively sampled, andthe number of “1” and the number of “0” in the 100 bits are counted.When an absolute difference between the two numbers is smaller than apredetermined threshold (e.g., 30), the alignment loop state machine 354is in a state “2”. The predetermined threshold can be determined asdesired instead of being the above value.

In a second method, the sampling signal S is directly observed. Forexample, when a continuous change of “0”, “1”, “0” and “1” occurs in thebitstream of the sampling signal S, it is determined that the state is“2”.

FIGS. 7A to 7C are a control process for a phase tuning signal in theedge alignment method according to one embodiment of the presentinvention. The embodiment is explained based on an example of adjustinga sampling square wave signal inputted into a sampling circuit. Further,a smallest delay effect is achieved when minimum values of the first,second and third selection signals in the phase adjusting signal areemployed.

FIG. 7A shows a tuning method of a first tuning stage. In Step S710, thesecond and third selection signals are maintained at their minimumvalues. In Step S712, according to the sampling signal S, it isdetermined whether a current state is state “0”, “1” or “2”. Thecalibration process ends when it is confirmed that the state is state“2”, and the current first, second and third selection signals arecombined as the phase tuning signal.

When it is confirmed that it is state “1” in Step S712, the firstselection signal is subtracted by 1 in Step S714, and it is determinedwhether the current state is a state “0”, “1” or “2” in Step S716. StepS714 is iterated to further subtract the first selection signal by 1when the current state is a state “1”; Step S726 is performed to selectthe first selection signal when the current state is “0”; or thecalibration process ends when the current state is “2”, and the currentfirst, second and third selection signals are combined as the phasetuning signal.

When it is confirmed that the state is “0” in Step S712, the firstselection signal is added by 1 in Step S720, and it is again determinedwhether the current status is a state “0”, “1”, or “2” in Step S722.Step S720 is iterated to further add the first selection signal by 1when the current state is a state “0”; Step S724 is performed tosubtract the first selection signal by 1 when the current state is “1”,followed by determining the first selection signal in Step S726; or thecalibration process ends when the current state is “2”, and the currentfirst, second and third selection signals are combined as the phasetuning signal.

It is known from the descriptions associated with FIG. 7A that, theabove method employs the first tuning stage to tune the sampling squarewave signal until the phase of the sampling square wave signal fallsahead of the phase of the sampled square wave signal (status “0”).Further, the phase difference between the sampling square wave signaland the sampled square wave signal is already smaller than the minimumtuning range of the first tuning stage.

As previously described, when it is confirmed that the phase of thesampling square wave signal falls ahead of the sampled square wavesignal (i.e., when the status is “0”), the second tuning stage isemployed to further tune the sampling square wave signal. FIG. 7B showsa tuning method of a second tuning stage. In Step S730, the previousfirst selection signal is fixed and the third selection signal ismaintained at its minimum value. In Step S732, it is determined whetherthe current state is “0” or “2”. When the state is “2”, the calibrationprocess ends, and the current first, second and third selection signalsare combined as the phase tuning signal.

When it is confirmed that the state is “0” in Step S732, the secondselection signal is added by 1 in Step S734, and it is again determinedwhether the state is “0”, “1” or “2” in Step S736. Step S734 is iteratedto further add the second selection signal by 1 when the state is “0”;the first selection signal is subtracted by 1 in Step S738 when thestate is “1”, followed by determining the second selection signal inStep S740; or the calibration process ends when the state is “2”, andthe current first, second and third selection signals are combined asthe phase tuning signal.

It is known from the descriptions associated with FIG. 7B that, theabove method employs the second tuning stage to tune the sampling squarewave signal until the phase of the sampling square wave signal fallsahead of the phase of the sampled square wave signal (state “0”).Further, the phase difference between the sampling square wave signaland the sampled square wave signal is already smaller than the minimumtuning range of the second tuning stage.

After determining the first and second selection signals, the thirdtuning stage is employed to delay the sampling square wave signal. FIG.7C shows a tuning method of a third tuning stage. In Step S750, theprevious first and second selection signals are fixed. In Step S752, itis determined whether the state is “0” or “2” according to the samplingsignal S. The calibration process ends when the state is “2”, and thecurrent first, second and third selection signals are combined as thephase tuning signal.

When it is confirmed the state is “0” in Step S752, the third selectionsignal is added by 1 in Step S754, and it is again determined whetherthe state is “0”, “1” or “2” in Step S756. Step S734 is iterated tofurther add the second selection signal by 1 when the state is “0”; thethird selection signal is determined in Step S758 when the state is “1”;or the calibration process ends when the state is “2”, and the currentfirst, second and third selection signals are combined as the phasetuning signal.

It is known from the descriptions associated with FIG. 7C that, theabove method employs the third tuning stage to tune the sampling squarewave signal until the phase of the sampling square wave signal fallsbehind the phase of the sampled square wave signal (status “1”), as wellas when the phase difference between the sampling square wave signal andthe sampled square wave signal is already smaller than the minimumtuning range of the third tuning stage. The final determined first,second and third selection signals are combined as the phase tuningsignal.

It is demonstrated with the descriptions of FIGS. 7A to 7C that thesampling square wave signal is gradually tuned by the coarse tuningstage, the intermediate tuning stage and the fine tuning stage to obtainthe minimum value of the phase difference between the sampling squarewave signal and the sampled square wave signal.

It should be noted that a person skilled in the related art is notmandated to perform the tuning according to the methods in FIGS. 7A to7C. Alternatively, the phase tuning signal may be sequentially changedfrom a minimum value to a maximum value, and a current state can bedetermined directly according to the sampling signal S. An optimal phasetuning signal is then selected from multiple phase tuning signalscorresponding to the state “2”. That is to say, when the phase tuningsignal is p-bit, the phase tuning signal is changed from small to largesuch that the sampling signal S determines 2^(p) states, so as to obtainan optimal phase tuning signal.

Further, to prevent a malfunction of the edge alignment apparatus of thepresent invention of aligning a rising edge of a sampling signal with afalling edge of a sampled signal, two methods are provided by thepresent invention to prevent such malfunction of the edge alignmentapparatus.

As the calibration process starts, it is possible that a rising edge ofthe sampling signal is coincidentally aligned with a falling edge of thesampled signal such that the state is determined as “2”. At this point,the phases of the two square wave signals are first tuned to bedifferent, followed by performing the methods from FIG. 7A to 7C forcalibration to ensure that the two rising edges of the two square wavesignals are aligned.

Another method provided by the present invention to prevent the abovemalfunction is by changing a duty cycle of one of the square wavesignals. When the alignment loop state machine 354 confirms that thesampling square wave signal and the sampled square wave signal are inthe same phase and determines the status as “2”, the sampling method ofthe sampling unit 352 is further changed to change the sampling squarewave signal as the sampled square wave signal and the sampled squarewave signal as the sampling square wave signal.

In the event that the alignment loop state machine 354 still determinesthe state as “2” after changing the sampling method of the sampling unit352, it is confirmed that the two square wave signals are in the samephase. Conversely, when the alignment loop state machine 354 determinesthat the state is “0” or “1” after changing the sampling method of thesampling unit 352, it is confirmed that the two square wave signals havea 180-degree phase difference, i.e., the rising edge of the samplingsignal is aligned with the falling edge of the sampled signal.

It is illustrated with the embodiments that, a method and associatedapparatus for clock-data signal edge alignment are provided by thepresent invention. The clock-data edge signal alignment method andapparatus are suitable to edge alignment of signals in the GHz level,and are capable of facilitating an RFDAC to generate highly efficient RFoutput signals.

Furthermore, those skilled in the art will appreciate that the severalmodules, functional units, etc. (collectively “components”) depicted inthe drawings and described herein may be implemented in hardware orsoftware or a combination thereof. In hardware, the components may beimplemented as, e.g., application specific integrated circuits (ASICs)including appropriate registers, I/O and processing functionality,and/or processors with associated memory for storing logic instructionswhich, when executed by the processor, perform the functions described,or any other like hardware implementation.

While the invention has been described by way of example and in terms ofthe preferred embodiments, it is to be understood that the invention isnot limited thereto. On the contrary, it is intended to cover variousmodifications and similar arrangements and procedures, and the scope ofthe appended claims therefore should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements and procedures.

What is claimed is:
 1. An apparatus for signal edge alignment,comprising: a signal source that generates a first square wave signaland a second square wave signal; a phase delay circuit that receives thefirst square wave signal and the second square wave signal, andgenerates a delayed version of the first square wave signal and adelayed version of the second square wave signal according to a phasetuning signal; a data circuit, that generates a third square wave signalaccording to the delayed version of the second square wave signal; and aphase calibration circuit that receives the third square wave signal andthe first square wave signal, and generates at the least one phasetuning signal to the phase delay circuit for tuning a phase differencebetween the delayed version of the first square wave signal and thedelayed version of the second square wave signal, such that a signaledge of the third square wave signal aligns with a signal edge of thefirst square wave signal; wherein, the first square wave signal, thesecond square wave signal and the third square wave signal have a samefrequency, and wherein the data circuit generates digital signals of aplurality of bits, and the third square wave signal is one of thedigital signals, such that a radio-frequency digital-to-analog converter(RFDAC) receives the digital signals and the delayed version of thefirst square wave signal to generate an RF signal.
 2. The apparatusaccording to claim 1, wherein the phase delay circuit comprises: a firstphase delay unit that receives the first square wave signal and a firstphase tuning signal to generate the delayed version of the first squarewave signal; and a second phase delay unit that receives the secondsquare wave signal and a second phase tuning signal to generate thedelayed version of the second square wave signal.
 3. The apparatusaccording to claim 1, wherein the second square wave signal and thedelayed version of the second square wave signal are in a same phase,and the phase delay circuit comprises a first phase delay circuit forreceiving the first square wave signal and the at least one phase tuningsignal to generate the delayed version of the first square wave signal.4. The apparatus according to claim 3, wherein the first phase delayunit comprises: a first tuning stage that receives the first square wavesignal and delaying the first square wave signal according a firstportion of the at least one phase tuning signal to generate a firstoutput clock signal; a second tuning stage that receives the firstoutput clock signal and delays the first output clock signal according asecond portion of the at least one phase tuning signal to generate asecond output clock signal; and a third tuning stage that receives thesecond output clock signal and delays the second output clock signalaccording to a third portion of the at least one phase tuning signal togenerate the delayed version of the first square wave signal.
 5. Theapparatus according to claim 4, wherein the first tuning stage is acoarse tuning stage, the second tuning stage is an intermediate tuningstage, and the third tuning stage is a fine tuning stage.
 6. Theapparatus according to claim 1, wherein the first square wave signal andthe delayed version of the first square wave signal are in a same phase,and the phase delay circuit comprises a second delay unit that receivesthe second square wave signal and the at least one phase tuning signalto generate the delayed version of the second square wave signal.
 7. Theapparatus according to claim 6, wherein the second phase delay circuitcomprises: a first tuning stage that receives the second square wavesignal and delays the second square wave signal according a firstportion of the at least one phase tuning signal to generate a firstoutput clock signal; a second tuning stage that receives the firstoutput clock signal and delays the first output clock signal according asecond portion of the at least one phase tuning signal to generate asecond output clock signal; and a third tuning stage that receives thesecond output clock signal and delays the second output clock signalaccording to a third portion of the at least one phase tuning signal togenerate the delayed version of the second square wave signal.
 8. Theapparatus according to claim 7, wherein the first tuning stage is acoarse tuning stage, the second tuning stage is an intermediate tuningstage, and the third tuning stage is a fine tuning stage.
 9. Theapparatus according to claim 1, wherein the phase calibration circuitcomprises: a sampling circuit that receives the third square wave signaland the delayed version of the first square wave signal to generate asampling signal; and an alignment loop state machine that receives abitstream in the sampling signal, changes the at least one phase tuningsignal when the bitstream is not metadata, and stops changing the atleast one phase tuning signal when the bitstream is metadata.
 10. Amethod for signal edge alignment, comprising: a) receiving a firstsquare wave signal and a second square wave signal; b) generating adelayed version of the first square wave signal and a delayed version ofthe second square wave signal according to at least one phase tuningsignal; c) sampling the delayed version of the second square wave signalaccording to the delayed version of the first square wave signal togenerate a sampling signal; and d) changing the at least one phasetuning signal and returning to step (b) when a bitstream in the samplingsignal is not metadata, and stopping changing the at least one phasetuning signal when the bitstream is metadata, wherein the at least onephase tuning signal comprises a first selection signal, a secondselection signal and a third selection signal.
 11. The method accordingto claim 10, wherein in a first state or in a second state, thebitstream is not metadata; and in a third state the bitstream ismetadata, the step of changing the at least one phase tuning signalchanges the first selection signal and comprises: maintaining the secondselection signal and the third selection signal at a minimum value; whenin the third state, ending a process of the method; when in the firststate, sequentially increasing the first selection signal until thefirst selection signal corresponds to the second state, and subtractingthe first selection signal by one (1) to become a determined firstselection signal; or, sequentially increasing the first selection signaluntil the first selection signal corresponds to the third state, andending the process; and when in the second state, sequentiallydecreasing the first selection signal until the first selection signalcorresponds to the first state to become the determined first selectionsignal; or sequentially decreasing the first selection signal until thefirst selection signal corresponds to the third state, and ending theprocess; wherein, when ending the process, the at least one phaseselection signal is formed according to the first selection signal, thesecond selection signal and the third selection signal.
 12. The methodaccording to claim 10, wherein when it is first determined to be in thethird state, changing the delayed version of the first square wavesignal and the delayed version of the second square wave signal so thatit is corresponding to the first state or the second state, and step (a)is again performed to prevent a malfunction.
 13. The method according toclaim 10, wherein: when it is first determined as the third state,changing the delayed version of the second square wave signal and thedelayed version of the first square wave signal to have different dutycycles, and sampling the delayed version of the first square wave signalaccording to the delayed version of the second square wave signal; whenit is confirmed that it is maintained at the first state or the secondstate, the malfunction is confirmed; and when it is confirmed that it isthe first state or the second state, to be entered, the malfunction isconfirmed.
 14. The method according to claim 13, wherein the step ofchanging the at least one phase tuning signal changes the secondselection signal and comprises: maintaining the determined firstselection signal, and maintaining the third selection signal at theminimum value; when in the third state, ending the process; and when inthe first state, sequentially increasing the second selection signaluntil the second selection signal corresponds to the second state, andsubtracting the second selection signal by one (1) to become adetermined second selection signal; or, sequentially increasing thesecond selection signal until the second selection signal corresponds tothe third state, and ending the process; wherein, when ending theprocess, the at least one phase selection signal is formed according tothe first selection signal, the second selection signal and the thirdselection signal.
 15. The method according to claim 14, wherein the stepof changing the at least one phase tuning signal changes the thirdselection signal and comprises: maintaining the determined firstselection signal and the determined second selection signal; when in thethird state, ending the process; and when in the first state,sequentially increasing the third selection signal until the thirdselection signal corresponds to the second state to become a determinedthird selection signal; or sequentially increasing the third selectionsignal until the third selection signal corresponds to the third state,and ending the process; wherein, when ending the process, the at leastone phase selection signal is formed according to the first selectionsignal, the second selection signal and the third selection signal. 16.A method for signal edge alignment, comprising: receiving a first squarewave signal and a second square wave signal; generating a delayedversion of the first square wave signal and a delayed version of thesecond square wave signal according to at least one phase tuning signal;sampling the delayed version of the second square wave signal accordingto the delayed version of the first square wave signal to generate asampling signal; and determining it is a first state or a second statewhen a bitstream in the sampling signal is not metadata, or determiningit is a third state when the bitstream is metadata; wherein, the atleast one phase tuning signal comprises p number of bits, and aplurality of third states are obtained after changing the at least onephase tuning signal 2^(P) times; and an optimal phase tuning signal isdetermined from a plurality of phase tuning signals corresponding to thethird states.